theory:sensor_technology:st22_adc_and_dac

*Analog to digital converters (ADC) and digital to analog converters (DAC) convert a signal which is continuous in time and amplitude to a signal which is discrete in time and amplitue and vice versa. This is a lossy process which has to be fast and efficient. Therefore, some insights are needed in how the cenversion is done.*

In modern sensor systems there is in almost all cases a node in the system where we go from analog signals to digital signals. In the end, the human readout is analog again, and assumed to represent the original analog value of the sensor. It is therefore a logical approach to think of all digital electronics as an equivalent analog circuit.

The reasoning is sketched in figure 1. The analog signal that comes in is $x(t)$. This signal is transformed by an Analog to Digital Converter (ADC) to a digital signal $X(z)$ which is discrete in time and amplitute. Discrete in time means te signal is sampled at fixed timeslots. Discrete in amplitude means that only a finite number of voltage levels can be represented in the digital domain (quantization). So, information is lost in de ADC. The digital filter will do some manipulation towards a digital signal $Y(z)$. The Digital to Analog Converter (DAC) converts it back to an analog signal $y(t)$.

Although information is lost in the ADC because of quantization in time and amplitude, we may think of the signal $y(t)$ as an analog filtered representation of $x(t)$. The question rises under what criteria this reasoning is valid. The *Shannon-Whitaker theorem* descibes this for the aspect of discretization in time. It says that the output signal is still a good representation when the sampling frequency is equal to at least twice the highest frequency content in the signal $x(t)$. The minimum allowable sampling frequency is also known as the *Nyquist rate*.

In figure 2 a symbolic representation is given of an analog to digital converter as a building block. What goes in is an analog signal. The ADC converts it to a binary representation that come out as a serial stream, or as some parallel bits (as drawn). A serial stream can be in an SPI or I^{2}C protocol. The ADC is an active component and so it needs a power suply $V_{dd}$.

To convert and anlog signal, two steps are needed:

- Sampling at given moments in time or intervals
- Conversion to discrete amplitude levels

With these two steps, the signal becomes discrete in time and amplitude.

*Discretization in time: sampling*

The first step is represented in figure 3. When the input $C$ is activated, the actual voltage $V_{in}$ is copied and frozen on the capacitor. The capacitor voltage is equal to $V_{in}$ and will remain equal until $C$ is activated again. At any moment after activation of $C$, the voltage is available for read-out as $V_{hold}$. There is a moment of *sampling* after which there is a *hold* phase.

There are two conventions that refer to the most common implemention in ADC circuits and the associated timer configurations in microcontrollers that have ADC's.

- On demand sampling - where a command activates the latch $C$ whenever we need a sample
- Continuous sampling - where a certain clock activates the latch $C$

Continuous sampling is normally done at equidistant *intervals*. This means that between two samples there is always a period $\Delta t = T$. We call $T$ the sampling interval based on which we can speak of the *sample rate* $f_{s}$

\begin{equation} f_{s}=\frac{1}{T}. \end{equation}

*Discretization in amplitude: quantization*

After sampling (and holding the value), there is the phase of *conversion* in which the captured voltage level is converted to a certain digital representation. This is in almost all cases at equidistant levels. For example, we can subdivide the amplitude range of interest, let's say $0V$ to $5V$ into 256 voltage levels. This would mean that every step represents roughly $19.5mV$. The number 256 is not a random number: it means we can represent all numbers as an 8-bit value. In general, the number of levels $n$ that can be represented by $N$ bits is equal to $n = 2^{N}$.

These numbers will represent voltage levels. When mapping the input range onto a voltage range from $V_{ref-}$ to $V_{ref+}$, each interval $\Delta V$ will be

\begin{equation}
\Delta V=\frac{V_{ref+}-V_{ref-}}{2^{N}}
\end{equation}
which becomes $\Delta V \approx 19.5mV$ for $V_{ref-}=0V$, $V_{ref+}=5V$ and $N=8~bits$ as seen in the example before. In figure 4 there is an example for $N=3~bits$ resulting into 8 levels. In that case $\Delta V$ becomes $1/8=0.125$ of the full range. The first level, captured by the binary value $000$, can be the result of any input value between $0V_{ref}$ and $0.125V_{ref}$. The binary value $001$ (we speak of the *least significant bit* or simply *lsb*) represents input voltages between $0.125V_{ref}$ and $0.250V_{ref}$. We can also say that the *lsb* is $0.125V_{ref}$. There is also a *most significant bit* or *msb* that represents whether an input voltage is in the range above or below $0.5V_{ref}$. The *msb* can also be seen as a sign-bit when we have a symmetrical input window.

There is always a residual error in the quantization process. We map the analog value onto discrete levels. The error is called *quantization noise* and the maximum instantaneous value is between $-0.5~\Delta V$ and $+0.5~\Delta V$. So the amplitude of the quantization noise is equal to the resolution $\Delta V$ and as such defined by the least significant bit.

In figure 4 the horizontal axes is expressed relative to $V_{ref-}$, and normalized to $V_{ref+}-V_{ref-}$ (the *full scale voltage range* $E_{FSR}$ which is also called *span*). Any input voltage outside the range $V_{ref-}$ to $V_{ref+}$ will result into either the lowest or highest binary representation respectively. We say that the signal is outside the ADC range and it has clipped.

The optimization of the signal range to the available sample window of an ADC is a process we do manually in a digital SLR camera. In figure 5 we see the histograms as available in Photoshop or on the camera display in more professional cameras. What we do in fact, is to map the light intensity distribution of the current situation to the range that the CCD sensor can handle.

*Conversion techniques*

To pick the right bit sequence for every analog level sounds easy: we could use $N$ comparators for an $N~bit$ ADC and define $N$ decision levels wih resistor arrays. The *msb* is generated by a comparator with a decision level exactly in the middle of the input range. This technique would be a *flash converter* or *parallel converter*. However, this is not the right procedure. Although such an ADC would be fast, the complexity goes up with $N$ and we will have serious amplitude noise from imbalances in the resistor arrays. Therefore, many techniques have been developed that have a better scalability.

A better solution is the *integrating ADC* of figure 6. The principle is based on the integration of a reference voltage $V_{ref}$ while measuring the time $T_{int}$ it takes to reach a level equal to $V_{in}$. This is called a *single slope* integration. The integrator voltage at time $t$ after the integration started is
\begin{equation}
V_{int}(t) = (V_{ref} / \tau) \cdot t
\end{equation}
with $\tau$ the characteristic integration time defined by $R$ and $C$. So, when $V_{int} = V_{in}$ we have found $T_{int}$ which is then the actual $t$. So the relation between the measured integration time $T_{int}$ and the volatge $V_{in}$ that must have been at the input is
\begin{equation}
V_{in} = V_{ref} \cdot \frac{T_{int}}{ \tau}.
\end{equation}

All ADC's will have a certain *conversion time*. For the single-slope integration ADC we can understand that the conversion time we have to take into account is equal to the longest integration time which is $\tau$. The basic advantage of the integrating ADC is that time can be measured relatively easy and with low timing noise (jitter) in standard microcontrollers.

Besides the single-slope ADC there are improved techniques like the *dual-slope* ADC, which is slower but has a higher precision. Other well-known ADC techniques worth investigating are:

- Sigma-delta conversion
- Successive approximation

To summarize, what is important in ADC selection and configuration is

- The number of bits that defined the resolution
- The sample rate that must satisfy the Nyquist rate $f_{sample} \geq f_{highest}$
- The signal range that must optimally use the input window for the best resolution
- Sample and hold behaviour to make constant voltage during conversion
- Stable reference voltages
- Conversion time taken into consideration with respect to sample rate
- Stable conversion timing (low jitter)

Digital to analog conversion is needed to close a measurement loop in a sensor/actuator system. In such a system, the DAC can function as a trigger or function generator to disturb the environment while measuring the response on this disturbace. The system of figure 7 is needed then. Now we have a *closed-loop* system which is different from an *open loop*, or *feed-forward* system.

The block scheme of a digital to analog converter (DAC) is given in figure 8. These elements are needed in for example outputting digital audio (CD or MP3), motor control or signal generators.

To do this, we need an element that outputs an analog voltage based on a binary input. The voltage range must be defined, so this element needs two reference inputs: $V_{ref-}$ and $V_{ref+}$. We also have to make an agreement on how to map the binary code onto the output range. In figure 9, the eight levels that are available because of the proposed three bit system are mapped onto a voltage range from $0V$ up to $10V$ by the simple conversion $V_{out}=V_{ref-}+ (V_{ref+}-V_{ref-})n/8$.

The digital input can be supplied by a parallel input (8, 10, 12, 14 bits at once), or by a serial input using SPI or I^{2}C. In the serial case, the serial clock must be significant higher than the requested DAC conversion rate.

There are however completely different mechanisms to do digital to analog conversion. One example is *pulsewidth modulation* as visualized in figure 10. The advantage of this method is that it only needs a single bit on a pin that can handle $0$'s and $1$'s only. Consider a microcontroller that has an output pin on which we put a square wave. If the square wave is symmetrical, meaning it is high for the same time it is low, we speak of a *duty-cycle* of 50%. The average voltage on that pin is 50% of the level we would have when outputting a high level only. When connecting an LED to that pin, we would see half of the intensity. So, by tuning the duty cycle, we can dim the LED. We call this a *pulsewidth modulated output*, or short *PWM*. In combination with a low-pass filter, we can create voltage levels at many analog levels. The number of levels is defined by the precision in timing.

In normal cases, PWM is implemented with a constant period, but with controllable duty-cycle. If the timing is controlled with an 8-bits counter, the PWM will have 256 levels because the duty cycle can be controlled in 256 steps. With optimum low-pass filtereing, the output voltage for an N-bit PWM DAC is

\begin{equation} V_{out}=V_{ref-}+(V_{ref+}-V_{ref-}) \frac{n}{2^{N}} \end{equation}

because the duty cycle is controlled as $n/2^{N}$

These are the chapters for the Sensor Technology course:

- Chapter 1: Measurement Theory
- Chapter 2: Measurement Errors
- Chapter 3: Measurement Domains
- Chapter 4: Circuits, Graphs, Tables, Pictures and Code
- Chapter 5: Basic Sensor Theory
- Chapter 6: Sensor-Actuator Systems
- Chapter 7: Modelling
- Chapter 8: Modelling: The Accelerometer - example of a second order system
- Chapter 9: Modelling: Scaling - why small things appear to be stiffer
- Chapter 10: Modelling: Lumped Element Models
- Chapter 11: Modelling: Finite Element Models
- Chapter 13: Modelling: Systems Theory
- Chapter 14: Modelling: Numerical Integration
- Chapter 15: Signal Conditioning and Sensor Read-out
- Chapter 16: Resistive Sensors
- Chapter 17: Capacitive Sensors
- Chapter 18: Magnetic Sensors
- Chapter 19: Optical Sensors
- Chapter 20: Actuators - an example of an electrodynamic motor
- Chapter 21: Actuator principles for small speakers
- Chapter 22: ADC and DAC
- Chapter 23: Bus Interfaces - SPI, I
^{2}C, IO-Link, Ethernet based ← Next - Appendix A: Systematic unit conversion
- Appendix B: Common Mode Rejection Ratio (CMRR)
- Appendix C: A Schmitt Trigger for sensor level detection

theory/sensor_technology/st22_adc_and_dac.txt · Last modified: 2017/10/10 18:46 by glangereis